Electrostatic performance

ESD Control technology.

Elect Nano develops ESD-safe materials for applications where surface resistance uniformity, low particle generation, dimensional control, thermal exposure, and stable dissipative behavior all matter. The platform is intended for semiconductor handling, electronics manufacturing, RF hardware, fixtures, trays, carriers, and protective components.

ESD material design

Static control, molded uniformity, and clean technical surfaces.

Elect Nano ESD-control materials use discrete CNT technology to create static-dissipative compounds for semiconductor, electronics, defense, and space hardware where conductivity must be paired with cleanliness, dimensional control, thermal performance, and surface quality.

Controlled dissipation

Surface and volume resistance tolerance selected around part geometry and handling risk.

Uniform conductive network

Discrete CNT dispersion reduces local hot spots and improves molded-part consistency.

Low-particle surfaces

Low-loading dCNT and specialty reinforcing filler packages reduce fiber sloughing and roughness concerns.

Inspection-ready finish

Stable black surfaces improve gray-value uniformity and laser marking readability.

<1 decade

surface-resistance variance across mapped dCNT ESD molded parts

100%

ESD protected coverage across all mapped areas with dCNT technology

0.754 microns

MPPO LP TGF30 measured surface roughness, Sa

270°C

LCP ESD TGF40 rated for solder reflow ovens

Material comparison

Why discrete CNTs change ESD material design.

Conventional conductive fillers partially achieve the resistance target while creating new problems in surface finish, stiffness, particulate behavior, and molded-part uniformity. Elect Nano designs ESD materials around the full part-level response, including surface finish, processability, and electrical consistency.

Scanning electron microscope image of a discrete CNT ESD material

Discrete CNTs

Tunable ESD control without fiber-dominated behavior.

Discrete CNT networks are used to create low-loading conductive pathways designed for uniform, static-dissipative response across molded parts.

Conductivity control

High

Filler loading

Ultra-low

FPM risk

Ultra-low

Surface finish

Excellent

  • Precise, tunable electrical conductivity
  • Uniform isotropic mechanical response compared with oriented fiber systems
  • Ultra-low filler loadings possible due to strong percolation
  • No sheathing or sloughing mechanism from reinforcing fibers
  • Uniform surface finish and strong laser marking contrast

JEDEC tray evidence

Surface resistance uniformity across molded geometry.

ESD material selection is not only about hitting an average resistance value. The useful question is whether the tray, carrier, or fixture stays within the safe range across the part geometry and flow path.

Interactive log resistance map

LCP ESD loading 2

Mean resistance

7.38E+05 ohm

Lower-resistance dissipative pathway with narrow part-to-part variation.

ESD control range1E+04 to 1E+11 ohmHigh resistanceToo conductiveSurface Resistance (Ohms)1E+21E+41E+61E+81E+101E+12104080120160Distance from gate (mm)
Material
Log trans mean
Log trans range
Protected area
LCP ESD loading 1
3.41E+08
4.91E+00
100%
LCP ESD loading 2
7.38E+05
2.83E+00
100%
Carbon fiber
4.51E+05
2.90E+08
20%

Tray protection comparison

dCNT trays protect the full mapped surface.

Surface resistance maps are most useful when they are translated into protected tray area. The comparison below highlights how Elect Nano dCNT JEDEC trays maintain protected ESD behavior across the mapped surface, while the carbon fiber reference protects only a limited portion of the tray.

Elect Nano dCNT JEDEC tray

Mapped tray area remains inside the protected ESD window.

Discrete CNT dispersion supports a continuous dissipative network across the usable tray surface, reducing unprotected regions created by local resistance deviations.

Interactive protected-area overlay

Elect Nano dCNT versus carbon fiber JEDEC trays.

Graphical comparison of Elect Nano dCNT JEDEC trays versus carbon fiber JEDEC trays

Surface quality

ESD performance must survive the surface inspection.

In semiconductor and electronics handling parts, static control is evaluated alongside surface finish, visible defects, particle risk, color uniformity, and marking quality.

Measured roughness comparison

67% lower Sa

MPPO LP TGF30 measured 0.754 microns Sa versus 2.270 microns Sa for the MPPO LP carbon fiber reference.

MPPO low-particle thin glass fiber roughness field

Surface roughness

0.754 microns Sa

MPPO LP TGF30

Thin glass fiber and dCNT formulation route used for smoother low-particle molded surfaces.

MPPO carbon fiber roughness field

Surface roughness

2.270 microns Sa

MPPO LP CF

Carbon fiber reference surface with higher measured arithmetic mean roughness.

Color uniformity and marking

Stable gray value improves inspection and traceability.

Uniform conductive networks support more consistent black surfaces, cleaner visual inspection, and stronger laser-marking contrast than fiber-dominated surfaces with exposed or directionally aligned filler.

Gray value profile

dCNT versus carbon fiber surface consistency.

Surface finish color uniformity comparison plot
Laser marked QR code contrast reference

Laser marking readability

Strong contrast supports traceability on molded ESD parts and inspection coupons.

Laser marking surface contrast map

Surface response mapping

Full-field imaging makes gray-value variation and mark quality easier to compare between formulations.

Product family

ESD platforms across bake-temperature requirements.

Elect Nano dCNT ESD compounds can be positioned by the thermal stability of the base resin, giving technical teams a continuous selection from lower-temperature parts such as shipping carriers, FOUPs, and burn-in test sockets to ultra high-temperature JEDEC trays rated for solder interconnect reflow ovens.

View ESD materials
100°C
150°C
200°C
250°C
285°C

Selected platform

270°C

LCP ESD TGF40

Rated for solder reflow ovens and high-temperature precision molded hardware

Application fit

Where ESD-control materials need more than conductivity.

The right ESD material depends on geometry, contact surfaces, thermal exposure, cleanliness requirements, mechanical targets, and the measurement method used for foreign particulate matter release.

Semiconductor trays and carriers

Use ESD compounds when JEDEC trays, fixture surfaces, or handling components need controlled dissipative behavior across the usable contact area.

Low-particle molded fixtures

Thin-glass and dCNT platforms are positioned for cleanroom components where fiber sloughing, surface roughness, and foreign particulate matter must be minimized.

High-temperature electronics hardware

dCNTs in MPPO, PESU, LCP, and PEEK base resins give designers options when static control must be paired with stiffness, toughness, and thermal stability.

Laser-marked technical parts

Uniform black surfaces and stable gray values can improve readable marking, traceability, and inspection compared with variable fiber-filled surfaces.

Define the resistance tolerance

Confirm the target surface and volume resistance, charging source, static dissipation pathway, test method, and fixture geometry.

Select the resin platform

Choose ABS, PC, PET, COC, MPPO, PESU, LCP, PEEK, TPU, or a custom matrix around temperature and mechanical constraints.

Validate on molded samples

Map resistance, surface finish, roughness, particle risk, and marking response on the actual sample format.

Screen thermal fit

Align bake temperature, HDT, dimensional stability, and processing window before design lock.

Control cleanliness risk

Evaluate sloughing, surface defects, and roughness alongside conductivity rather than treating them as secondary issues.

Move into product selection

Use the ESD-safe materials portfolio as the starting point for samples, plaques, and application-specific development lots.

Material sample review

Evaluate ESD Control for your application.

Share the performance target, process constraints, and use environment. Elect Nano can help define a practical evaluation plan.