The Fixture Is Part of the Process: Why Static Control Belongs in Semiconductor Material Design

Static charge is not a side problem in semiconductor manufacturing. It is one of those invisible process variables that can quietly turn a well-controlled facility into a yield-loss machine—and unlike a broken sensor or a drifting etch rate, it rarely announces itself until the damage is done.1

Every FOUP, burn-in socket, JEDEC tray, carrier, nest, shuttle, end effector, and test fixture is doing more than holding a part. It is touching, sliding, lifting, separating, aligning, and transporting devices that are increasingly sensitive to electrostatic fields, electrostatic discharge, and particle contamination. A fixture made from the wrong material can become a charge generator, a particle attractor, or a discharge source—sitting directly inside the process flow, invisible in the process spec.

The argument here is straightforward: static control should not be treated as a feature added to a fixture after the design is finished. It should be engineered into the material from the beginning—alongside mechanical performance, thermal stability, chemical compatibility, and dimensional tolerance.

Why Static Charge Builds Up

Static charge is created whenever two materials come into contact and then separate.2 In a semiconductor facility, that happens constantly and unavoidably.

A tray pocket contacts a molded package. A wafer carrier contacts guide rails. A socket lid closes against a device. A robotic end effector picks, places, slides, and releases. A shipping fixture vibrates during transport. A polymer surface slides against another polymer surface. Each of these events can transfer charge—and the direction and magnitude of transfer depend on the triboelectric properties of the materials involved.

The problem becomes more severe because many materials used in precision fixtures are excellent insulators. High-performance polymers are selected for good reasons: dimensional stability, chemical resistance, low weight, high-temperature capability, moldability, and cleanliness. Electrically insulating polymers can hold charge for long periods of time, and once charged, they may not provide any safe pathway for dissipation.

Electrostatic discharge (ESD) is the rapid transfer of charge between objects at different electrical potentials. The ESD Association (ESDA) defines it as a rapid, spontaneous transfer of electrostatic charge induced by a high electrostatic field.2 But in semiconductor manufacturing, the issue is broader than the discharge event itself. Static charge creates electric fields, attracts particles, disturbs automation alignment, and increases contamination risk—often well before a visible or measurable discharge occurs. SEMI has specifically noted that static charge buildup in semiconductor manufacturing is unavoidable and must be controlled throughout manufacturing stages.1

The Consequences Are Bigger Than a Failed Device

The obvious concern is device damage. ESD can cause immediate catastrophic failure, and it can also create latent damage that escapes initial test and surfaces later as field failure.3 That risk has driven decades of standards, handling procedures, packaging rules, protected workstations, grounding systems, ionizers, and material specifications.

But in advanced semiconductor manufacturing, static charge also creates a second problem: electrostatic attraction.

Charged wafers, reticles, packages, trays, and fixture surfaces attract particles. SEMI E78 exists specifically because static charge and electric fields can negatively affect productivity in semiconductor manufacturing equipment—including through both ESD events and electrostatic attraction to surfaces. A particle that would otherwise drift past a surface can be pulled toward it by an electrostatic field. Once it lands, it may be difficult to remove. ESDA fab guidance describes how charged particles can bond to wafer surfaces, with the bonding force becoming stronger for smaller particles—which is exactly the wrong direction as device geometries continue to shrink.4

That makes ESD control a yield issue, a contamination issue, a reliability issue, and an automation issue simultaneously. It is not a compliance checkbox.

How the Industry Controls Static Today—and Where Each Approach Falls Short

The industry has developed practical ways to address static charge, and most of them work—within limits.

Grounding and bonding are essential for conductive objects. If a metal tool or conductive fixture is grounded, charge has a safe pathway out. But grounding only works when the material can actually conduct charge to a ground point. An insulating polymer surface can remain charged even when it is bolted to a grounded piece of equipment.

Ionization is widely used to neutralize charge on insulating surfaces and is effective in open environments. The limitation is that ionization depends on geometry, airflow, emitter maintenance, balance, and line-of-sight access. It is a process control tool—a useful one—but not a substitute for a properly designed material.

Humidity control can reduce charge generation in some environments. But semiconductor manufacturing and packaging operations often have strict moisture requirements, and many devices, packages, and processes cannot rely on elevated humidity as a primary static-control strategy.

Topical antistatic coatings can work initially, but they introduce their own concerns: wear, scratching, extractables, cleaning compatibility, adhesion loss, and performance drift. If the coating is the only conductive pathway, every abrasion event becomes an ESD reliability event.

Migrating antistatic additives can lower surface charging, but many depend on moisture and surface migration. In cleanroom and semiconductor environments, anything that migrates, blooms, or changes with humidity deserves close scrutiny.

Carbon black, graphite, and carbon fiber filled polymers are common because they can create permanent conductivity. They are also imperfect for reasons that will be discussed in detail below—particularly around particle generation and ionic contamination.56

None of these approaches is complete by itself. In most real facilities, they are layered together. The material is the foundation.

Measuring ESD Performance: Why Surface Resistance Is Not the Same as Surface Resistivity

One of the most persistent sources of confusion in ESD material selection is the difference between resistance and resistivity—and it matters more than it might seem.7

Surface resistivity is expressed in ohms per square (Ω/□). It is a material property, independent of geometry—or at least, it is supposed to be. In practice, surface resistivity is calculated from a resistance measurement using a specific probe geometry, and then normalized to a "square" of material. The concept comes from the sheet resistance formalism used in thin-film electronics, where it makes physical sense. Applied to bulk polymer compounds and molded parts, it is far less rigorous.

Surface resistance, measured in ohms (Ω), is what ANSI/ESD STM11.11 actually specifies. It is a direct measurement between defined electrode geometries on a planar material sample. ANSI/ESD STM11.12 covers volume resistance of planar materials, also in ohms. These are the methods the ESDA recommends for material qualification—and for good reason. They describe the electrical behavior of a specific geometry under a specific test configuration, rather than a derived material constant.

The practical problem with ohms-per-square as a qualifying metric is that it encourages comparisons that do not hold up. A material reported at 10⁸ Ω/□ sounds well-defined, but the number means little unless you know the probe configuration, the applied voltage, the conditioning environment, and whether the measurement was made on a planar coupon or a molded part. Data sheets that lead with resistivity often obscure more than they reveal.

For a semiconductor fixture—a burn-in socket, a JEDEC tray, a carrier pocket—the relevant question is not what the resistivity of the compound is, but what the resistance of the molded article will be in service. Those are different questions. A material with good resistivity on a flat coupon may show very different behavior at a rib junction, a gate location, a thin wall, or a high-wear contact surface. Volume resistance (STM11.12) becomes particularly important for parts that are grounded only through a defined contact point, since it characterizes the electrical pathway through the bulk of the part.

The standards reflect this. IEC 61340-5-1:2024 requires that ESD control program requirements address the resistance of items in the protected area—not abstract material resistivity values. JESD625C similarly focuses on the electrical behavior of packaging and handling materials in defined configurations. Material qualification should follow the same logic: measure the part, in the test configuration that reflects how it will be used.

The ESD-Safe Range—and When It Needs to Be Narrower

The ESD Association categorizes materials by their electrical resistance:2

• Conductive: Surface resistance below 1 × 10⁴ Ω
• Dissipative: Surface resistance from 1 × 10⁴ Ω to less than 1 × 10¹¹ Ω
• Insulative: Surface resistance at or above 1 × 10¹¹ Ω

For most semiconductor fixture applications, the dissipative range—1 × 10⁴ to 1 × 10¹¹ Ω—is described as "ESD safe," in the sense that materials in this range can dissipate charge without acting as a low-impedance conductor. That seven-order-of-magnitude range is usefully broad for classification purposes. It is not very useful for material specification.

The right target within that range depends on how the fixture will be used in service—specifically, whether it is grounded, floating, or in an ionized environment. These three conditions require different strategies.

Grounded Fixtures

When a fixture or carrier is reliably grounded—bolted to a grounded table, connected through a conductive pathway to earth ground, or handled by a grounded operator through a wrist strap—lower resistance in the dissipative range is generally advantageous. A surface resistance in the 10⁴ to 10⁷ Ω range allows charge to drain quickly and predictably to ground when contact is made. The ground connection does the work; the material just needs to maintain a conductive path to it.

For burn-in sockets, test fixtures, and handler nests that are mounted to grounded equipment and make consistent mechanical contact, targeting the lower portion of the dissipative range often makes sense. The risk of targeting too low—dipping into the conductive range—is that very low-resistance parts can allow rapid discharge through the device under test rather than safely to ground. For sensitive CDM applications, even "conductive" fixtures can become a discharge path if the resistance is too low.8

Floating Fixtures

When a fixture is not reliably grounded—carried by an operator, moved on a non-grounded cart, or used in a process where the ground connection is intermittent—the situation changes. A floating fixture at 10⁵ Ω behaves differently than one at 10⁹ Ω. If charge builds up on a low-resistance floating fixture and a discharge path suddenly appears (the fixture contacts a grounded surface or a device), the charge can transfer rapidly. Targeting the middle portion of the dissipative range—10⁷ to 10⁹ Ω—slows the discharge rate enough to prevent damage even when grounding is inconsistent. JEDEC trays and shipping carriers in facilities where handling discipline cannot be perfectly controlled are good examples of applications where mid-range resistance is the right target, not the lowest achievable value.

Fixtures in Ionized Environments

Ionizing air systems neutralize surface charge by delivering balanced positive and negative ions to a surface. In an ionized environment, a fixture material does not need to dissipate charge through a resistive pathway—the ionizer is doing that work externally. This might seem to make the material resistance irrelevant, but it does not. Volume resistance still matters for charge that builds up within the bulk of the part rather than on its surface. And if the ionizer is ever offline, undersized, or blocked by geometry, the material resistance becomes the only remaining defense.

For fixtures that operate primarily in ionized environments, the target is often in the 10⁸ to 10¹⁰ Ω range—high enough to avoid rapid discharge events if a device contact occurs, but low enough to drain any residual charge over seconds or minutes without depending exclusively on the ionizer. Specifying toward the high end of the dissipative range also reduces the risk of the fixture acting as an unintended charge source for devices that pass through without ionizer coverage.

The broader point is this: "ESD safe" is not a material spec. It is a starting point. The material engineer's job is to identify the specific resistance window—often spanning two to three orders of magnitude rather than seven—that suits the grounding condition, device sensitivity, contact geometry, and process environment of the application.

Ionic Purity: The Problem Nobody Talks About Until Something Goes Wrong

Most ESD material discussions focus on resistance. Far fewer address ionic contamination—and in wet-contact semiconductor applications, this can be the more critical specification.

Conventional conductive fillers—carbon black in particular—are manufactured through high-temperature pyrolysis processes that can leave residual surface chemistry: sulfur-containing functional groups, acidic surface oxides, and adsorbed anions including sulfate (SO₄²⁻), chloride (Cl⁻), and nitrate (NO₃⁻).9 Cationic contamination (sodium, potassium, iron, and other metals) can be present as well, depending on feedstock and process controls. These residuals are typically measured in parts per million—adequate for many applications, but a significant concern for semiconductor wet processing.

Applications where ionic purity matters most include:

• Wet etch and chemical mechanical planarization (CMP) fixtures and carriers, where the part comes into direct contact with process chemicals and ultrapure water
• Single-wafer wet cleaning components, where ionic leaching into the rinse chemistry can cause metallic contamination on wafer surfaces
• Post-CMP brush contact and slurry delivery components, where residual anions can interact with process chemistry
• Electroplating and electrolytic deposition hardware, where ionic contamination in the bath affects film quality

In these environments, residual ionic contamination from fillers can leach into process chemistry at ppb (parts per billion) concentrations—well below detection by standard supplier testing, but sufficient to cause metal deposition, pitting, corrosion, or device failure. Ionic purity specifications for wet-contact polymer components in leading-edge semiconductor fabs are routinely written at the ppb level for individual anions and cations, requiring analytical methods such as ion chromatography (IC) and inductively coupled plasma mass spectrometry (ICP-MS) to verify.10

Carbon black, at typical loading levels needed to achieve target resistance in a polymer compound, introduces filler surface area and chemistry that can be difficult to clean to ppb ionic levels. The challenge is not just the filler itself but the compounding and molding process—any residual mold release, processing aid, or contamination picked up in the process can contribute to extractable ionic load.

Discrete, functionalized carbon nanotubes present a different profile. Because they achieve the target resistance network at much lower filler loading—often by an order of magnitude or more compared to carbon black—the total filler surface area per unit of compound is substantially lower, and the chemistry of the nanotube surface can be controlled through the functionalization process. This does not make ionic purity automatic; it still requires careful compound formulation, process controls, and validated extraction testing. But it creates a much more tractable path to ppb-level ionic cleanliness than high-loading carbon black systems.

For wet-contact fixture applications, ionic purity should be a first-tier specification alongside resistance target and base polymer selection—not an afterthought added after the material is already chosen.

Foreign Particulate Matter: The Hidden Cost of Traditional Conductive Fillers

Particle generation—foreign particulate matter, or FPM—is the other area where conventional ESD polymer solutions often force an uncomfortable tradeoff.

Carbon black works by creating a network of conductive particles within the polymer matrix. To achieve dissipative or conductive resistance levels, typical carbon black loading in a thermoplastic compound runs from roughly 5 to 20 percent by weight, depending on the polymer, the carbon black grade, and the target resistance. At those loadings, a significant fraction of carbon black particles are near or at the surface of the molded part. Particle generation from surface abrasion, wear at contact points, flexing, and handling is a documented concern. Texas Instruments has specifically noted that sloughing—the shedding of carbon particles from the compound—is a major disadvantage of carbon black systems, and can make carbon black composites unsuitable depending on handling requirements.5 Published research on injection-moldable ESD composites has similarly identified released carbon black particles as a risk to semiconductor performance and wafer contamination during contact and friction between wafers and carriers.6

Carbon fiber introduces a different but related FPM risk. Chopped carbon fiber is used in ESD polymer compounds both for electrical conductivity and for enhanced mechanical stiffness. The problem is that carbon fiber ends are exposed at machined or molded surfaces, and fiber fragments—typically 5 to 50 microns in length—can be released during wear, handling, or cleaning. In a cleanroom environment, a single carbon fiber fragment on a wafer surface is a defect. In a contact socket or carrier pocket, fiber fragments can interfere with electrical contact or damage device surfaces. Unlike spherical or irregular particles, fiber fragments can align with surface features and be difficult to detect and remove.

Graphite-filled systems share some of these concerns, particularly around particle generation under friction, and graphite platelets can be particularly problematic because of their tendency to smear across surfaces rather than being captured by cleanroom filtration.

How discrete functionalized carbon nanotubes differ

The FPM advantage of dCNT technology comes from two places: loading level and surface chemistry.

Because carbon nanotubes have extremely high aspect ratio—individual tubes can be hundreds or thousands of times longer than their diameter—a percolated conductive network can be formed at very low loading levels in the polymer matrix. Where carbon black might require 10 to 15 percent loading to reach the dissipative range, a well-dispersed dCNT system may achieve the same resistance target at 1 to 5 percent loading, or lower, depending on the polymer and nanotube characteristics.11 Less filler means less surface-exposed filler, and less surface-exposed filler means less material available for particle generation.

Functionalization is the second factor. Raw carbon nanotubes aggregate aggressively in polymer melts and are difficult to disperse uniformly. Functionalized nanotubes—with surface chemistry specifically designed to interact with the polymer matrix—disperse more completely and bond more effectively to the surrounding material. A well-bonded nanotube that is deeply embedded in the polymer matrix is far less likely to be released as a free particle than a loosely held carbon black agglomerate at a part surface.

The combination of low loading and effective matrix bonding does not eliminate FPM concerns entirely—no polymer compound is perfectly free of particle generation—but it addresses the root causes more directly than simply specifying a "low-dust" grade of carbon black or a shorter fiber length.

For applications where FPM is a primary qualification criterion—wafer carriers, FOUP interiors, reticle pods, cleanroom automation components, and test fixtures that operate in class 1 or class 10 environments12—this distinction is not marginal. It is frequently the difference between a material that passes particle qualification and one that does not.

The Standards Framework

The semiconductor and electronics industries have a well-developed standards framework for ESD control. The relevant standards establish not only what to control, but how to measure it—and the measurement methodology matters.

JESD625C covers requirements for handling electrostatic-discharge-sensitive devices and applies to devices susceptible to damage above specified HBM and CDM thresholds. IEC 61340-5-1:2024 provides requirements for establishing, implementing, and maintaining an ESD control program. ANSI/ESD S541 addresses packaging materials used to protect ESD-susceptible items through production, storage, and handling.

For material measurement, the key test methods are:

• **ANSI/ESD STM11.11** — surface resistance of planar materials, measured in ohms between concentric electrode rings at specified applied voltage
• **ANSI/ESD STM11.12** — volume resistance of planar materials, measured through the thickness of a sample
• **ANSI/ESD STM11.13** — two-point resistance measurement, listed by ESDA among product qualification laboratory methods13

These methods specify resistance—not resistivity. When a data sheet reports ohms-per-square without specifying the measurement configuration, that number cannot be directly compared to an STM11.11 or STM11.12 result. Material qualification for semiconductor fixture applications should specify which method applies, at what applied voltage, under what conditioning environment (temperature, humidity, time), and whether the measurement is on a flat coupon or the actual molded article.

That last point deserves emphasis. A semiconductor fixture is not a flat plaque. It has ribs, pockets, radii, hinges, gates, wear surfaces, and local thickness changes. A material must be engineered so the molded article—not just a test coupon—has the intended electrical behavior. Resistance can vary significantly between a nominal wall thickness and a thin rib, between a gate location and a far-flow location, and between a new part and one that has experienced fifty thermal cycles or five hundred insertions.

Where dCNT Materials Fit Best

The strongest applications for dCNT-enabled materials are those where conventional ESD solutions force tradeoffs that cannot be fully resolved with existing filler technology.

Burn-in sockets and test fixtures require dimensional precision, thermal stability, repeated actuation, and reliable electrical behavior at temperature. The resistance target needs to be maintained across the thermal cycle, not just at room temperature. Carbon black systems can shift resistance significantly over temperature excursions; nanotube networks tend to be more thermally stable.

JEDEC trays and package carriers need stable charge dissipation, low particle generation, good molded surface detail, and consistent handling through shipping, storage, and automated processing. Mid-range dissipative resistance (10⁷ to 10⁹ Ω) is often the right target for floating-use carriers.

FOUP, FOSB, and wafer carrier components are exposed to high-value wafers and strict contamination requirements. Some FOUP suppliers already offer ESD-rated shells or ESD material options, which reflects the industry's recognition that electrostatic charge accumulation in carriers must be managed.14 For wafer-contact surfaces inside these carriers, both FPM and ionic purity specifications apply.

Automation nests, end effectors, guides, and shuttles need to dissipate charge without creating new contamination or tolerance problems. In high-speed automated handling, the mechanical requirements are often as demanding as the electrical ones—and the material has to meet both without compromise.

High-temperature semiconductor packaging fixtures need ESD performance that holds up after thermal exposure, cleaning chemistry, and repeated use. Resistance drift over the service life of the fixture is a real concern and should be part of the qualification plan.

Wet-contact process components in etch, CMP, and cleaning applications need ionic purity specifications that conventional carbon black systems often cannot meet at required filler loading levels.

Designing to the Application, Not to a Category

The framing of "ESD-safe material" is not specific enough to design a semiconductor fixture. The useful specification includes:

• Target surface resistance and volume resistance (in ohms, per the applicable test method), with the electrode configuration and test conditions defined
• Whether the fixture will be grounded, floating, or operating in an ionized environment—and what that means for the resistance window
• Particle generation requirements, including test method and acceptable FPM count per contact event or per unit area
• Ionic purity requirements for extractable anions and cations, particularly for wet-contact applications, expressed in ppb with the extraction method specified
• Thermal stability of resistance over the service temperature range and cycle count
• Mechanical requirements: modulus, toughness, wear resistance, creep, dimensional tolerances
• Chemical compatibility: cleaning chemistry, process gases, handling fluids
• Base polymer selection: PEEK, PEI, LCP, PEKK, PPS, PPSU, or others depending on temperature and chemistry requirements

When those parameters are defined, material selection and development becomes a real engineering problem rather than a search for a catalog product. dCNT technology is useful for this type of problem precisely because the conductive network can be tuned—resistance target, loading level, polymer compatibility, thermal stability—within a development framework that also addresses ionic purity and FPM through the filler chemistry and loading approach.

The Bottom Line

As semiconductor devices become smaller, more sensitive, and more valuable, the materials used around them matter more. A tray is not just a tray. A socket is not just a socket. A carrier is not just a carrier. Every polymer fixture in the process is either helping control static charge or contributing to the problem—and "ESD safe" stenciled on a box does not answer the question of which one it is.

The industry understands grounding, ionization, packaging standards, protected areas, and ESD-safe handling. The next step is better material design: permanent, tunable ESD performance with controlled particle generation and ionic purity, built into the fixtures and components that touch sensitive devices every day.

Elect Nano's dCNT technology was developed for exactly that type of problem—where electrical performance, polymer processing, mechanical reliability, ionic cleanliness, and particle control all have to work together.

If you are designing FOUP components, burn-in sockets, JEDEC trays, carriers, automation fixtures, wet-contact process hardware, or custom semiconductor handling components, bring us the application. Tell us the polymer constraints, the resistance target and why that target was chosen, the process temperature, the grounding condition, the ionic purity requirement, and the failure mode you are trying to avoid. We will help translate that into a material development path.

Because in semiconductor manufacturing, static control is not just an ESD requirement. It is part of the process—and it belongs in the material.